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publication# 16493 rev: e amendment/ 0 issue date: november 1998 pal devices palce16v8 coml:h-5/7/10/15/25, q-10/15/25 ind:h-10/25, q-20/25 palce16v8z coml:-25 ind:-12/15/25 palce16v8 and palce16v8z families ee cmos (zero-power) 20-pin universal programmable array logic distinctive characteristics u pin and function compatible with all 20-pin pal ? devices u electrically erasable cmos technology provides recon?gurable logic and full testability u high-speed cmos technology 5-ns propagation delay for -5 version 7.5-ns propagation delay for -7 version u direct plug-in replacement for the pal16r8 series u outputs programmable as registered or combinatorial in any combination u peripheral component interconnect (pci) compliant u programmable output polarity u programmable enable/disable control u preloadable output registers for testability u automatic register reset on power up u cost-effective 20-pin plastic dip, plcc, and soic packages u extensive third-party software and programmer support u fully tested for 100% programming and functional yields and high reliability u 5-ns version utilizes a split leadframe for improved performance general description the palce16v8 is an advanced pal device built with low-power, high-speed, electrically- erasable cmos technology. it is functionally compatible with all 20-pin gal devices. the macrocells provide a universal device architecture. the palce16v8 will directly replace the pal16r8, with the exception of the pal16c1. the palce16v8z provides zero standby power and high speed. at 30-a maximum standby current, the palce16v8z allows battery-powered operation for an extended period. the palce16v8 utilizes the familiar sum-of-products (and/or) architecture that allows users to implement complex logic functions easily and ef?ciently. multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in pal devices. the equations are programmed into the device through ?oating-gate cells in the and logic array that can be erased electrically. the ?xed or array allows up to eight data product terms per output for logic functions. the sum of these products feeds the output macrocell. each macrocell can be programmed as registered or combinatorial with an active-high or active-low output. the output con?guration is determined by two global bits and one local bit controlling four multiplexers in each macrocell.
248 palce16v8 and palce16v8z families block diagram functional description the palce16v8 is a universal pal device. the palce16v8z is the zero-power version of the palce16v8. it has all the architectural features of the palce16v8. in addition, the palce16v8z has zero standby power and an unused product term disable feature for reduced power consumption. it has eight independently con?gurable macrocells (mc 0 - mc 7 ). each macrocell can be con?gured as registered output, combinatorial output, combinatorial i/o or dedicated input. the programming matrix implements a programmable and logic array, which drives a ?xed or logic array. buffers for device inputs have complementary outputs to provide user- programmable input signal polarity. pins 1 and 11 serve either as array inputs or as clock (clk) and output enable (oe ), respectively, for all ?ip-?ops. unused input pins should be tied directly to v cc or gnd. product terms with all bits unprogrammed (disconnected) assume the logical high state, and product terms with both true and complement of any input signal connected assume a logical low state. the programmable functions on the palce16v8 are automatically con?gured from the users design speci?cation. the design speci?cation is processed by development software to verify the design and create a programming ?le (jedec). this ?le, once downloaded to a programmer, con?gures the device according to the users desired function. the user is given two design options with the palce16v8. first, it can be programmed as a standard pal device from the pal16r8 series. the pal programmer manufacturer will supply device codes for the standard pal device architectures to be used with the palce16v8. the programmer will program the palce16v8 in the corresponding architecture. this allows the user to use existing standard pal device jedec ?les without making any changes to them. programmable and array 32 x 64 macro mc 0 macro mc 1 macro mc 2 macro mc 3 macro mc 4 macro mc 5 macro mc 6 macro mc 7 oe /i 9 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 8 i 1 C i 8 clk/i 0 16493e-1
palce16v8 and palce16v8z families 249 pal devices alternatively, the device can be programmed as a palce16v8. here the user must use the palce16v8 device code. this option allows full utilization of the macrocell. configuration options each macrocell can be con?gured as one of the following: registered output, combinatorial output, combinatorial i/o, or dedicated input. in the registered output con?guration, the output buffer is enabled by the oe pin. in the combinatorial con?guration, the buffer is either controlled by a product term or always enabled. in the dedicated input con?guration, it is always disabled. with the exception of mc 0 and mc 7 , a macrocell con?gured as a dedicated input derives the input signal from an adjacent i/o. mc 0 derives its input from pin 11 (oe ) and mc 7 from pin 1 (clk). the macrocell con?gurations are controlled by the con?guration control word. it contains 2 global bits (sg0 and sg1) and 16 local bits (sl0 0 through sl0 7 and sl1 0 through sl1 7 ). sg0 determines whether registers will be allowed. sg1 determines whether the palce16v8 will emulate a pal16r8 family or a pal10h8 family device. within each macrocell, sl0 x , in conjunction with sg1, selects the con?guration of the macrocell, and sl1 x sets the output as either active low or active high for the individual macrocell. the con?guration bits work by acting as control inputs for the multiplexers in the macrocell. there are four multiplexers: a product term input, an enable select, an output select, and a feedback select multiplexer. sg1 and sl0 x are the control signals for all four multiplexers. in mc 0 and mc 7 , sg0 replaces sg1 on the feedback multiplexer. this accommodates clk being the adjacent pin for mc 7 and oe the adjacent pin for mc 0 . figure 1. palce16v8 macrocell 1 1 0 x 1 0 *sg1 sg1 sl0 x dq q 1 0 1 1 0 x 1 1 1 0 0 0 0 1 v cc clk sl0 x oe to adjacent macrocell from adjacent pin 1 1 0 x 1 0 sl1 x i/o x 16493e-2 *in macrocells mc 0 and mc 7 , sg1 is replaced by sg0 on the feedback multiplexer.
250 palce16v8 and palce16v8z families registered output con?guration the control bit settings are sg0 = 0, sg1 = 1 and sl0 x = 0. there is only one registered con?guration. all eight product terms are available as inputs to the or gate. data polarity is determined by sl1 x. the ?ip-?op is loaded on the low-to-high transition of clk. the feedback path is from q on the register. the output buffer is enabled by oe . combinatorial con?gurations the palce16v8 has three combinatorial output con?gurations: dedicated output in a non- registered device, i/o in a non-registered device and i/o in a registered device. dedicated output in a non-registered device the control bit settings are sg0 = 1, sg1 = 0 and sl0 x = 0. all eight product terms are available to the or gate. although the macrocell is a dedicated output, the feedback is used, with the exception of pins 15 and 16. pins 15 and 16 do not use feedback in this mode. because clk and oe are not used in a non-registered device, pins 1 and 11 are available as input signals. pin 1 will use the feedback path of mc 7 , and pin 11 will use the feedback path of mc 0 . combinatorial i/o in a non-registered device the control bit settings are sg0 = 1, sg1 = 1, and sl0 x = 1. only seven product terms are available to the or gate. the eighth product term is used to enable the output buffer. the signal at the i/o pin is fed back to the and array via the feedback multiplexer. this allows the pin to be used as an input. because clk and oe are not used in a non-registered device, pins 1 and 11 are available as inputs. pin 1 will use the feedback path of mc 7 , and pin 11 will use the feedback path of mc 0 . combinatorial i/o in a registered device the control bit settings are sg0 = 0, sg1 = 1 and sl0 x = 1. only seven product terms are available to the or gate. the eighth product term is used as the output enable. the feedback signal is the corresponding i/o signal. dedicated input con?guration the control bit settings are sg0 = 1, sg1 = 0 and sl0 x = 1. the output buffer is disabled. except for mc 0 and mc 7 , the feedback signal is an adjacent i/o. for mc 0 and mc 7 , the feedback signals are pins 1 and 11. these con?gurations are summarized in table 1 and illustrated in figure 2. table 1. macrocell con?guration sg0 sg1 sl0 x cell con?guration devices emulated sg0 sg1 sl0 x cell con?guration devices emulated device uses registers device uses no registers 0 1 0 registered output pal16r8, 16r6, 16r4 100 combinatorial output pal10h8, 12h6, 14h4, 16h2, 10l8, 12l6, 14l4, 16l2 011 combinatorial i/o pal16r6, 16r4 1 0 1 input pal12h6, 14h4, 16h2, 12l6, 14l4, 16l2 111 combinatorial i/o pal16l8
palce16v8 and palce16v8z families 251 pal devices programmable output polarity the polarity of each macrocell can be active-high or active-low, either to match output signal needs or to reduce product terms. programmable polarity allows boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. it can also save demorganizing efforts. selection is through a programmable bit sl1 x which controls an exclusive-or gate at the output of the and/or logic. the output is active high if sl1 x is 1 and active low if sl1 x is 0.
252 palce16v8 and palce16v8z families figure 2. macrocell con?gurations d q q oe clk a. registered active low d q q oe clk b. registered active high c. combinatorial i/o active low d. combinatorial i/o active high e. combinatorial output active low v cc f. combinatorial output active high v cc adjacent i/o pin g. dedicated input notes: 1. feedback is not available on pins 15 and 16 in the combinatorial output mode. 2. this con?guration is not available on pins 15 and 16. note 1 note 1 note 2 16493e-2
palce16v8 and palce16v8z families 253 pal devices power-up reset all ?ip-?ops power up to a logic low for predictable system initialization. outputs of the palce16v8 will depend on whether they are selected as registered or combinatorial. if registered is selected, the output will be high. if combinatorial is selected, the output will be a function of the logic. register preload the register on the palce16v8 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. this feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. in addition, transitions from illegal states can be veri?ed by loading illegal states and observing proper recovery. security bit a security bit is provided on the palce16v8 as a deterrent to unauthorized copying of the array con?guration patterns. once programmed, this bit defeats readback and veri?cation of the programmed pattern by a device programmer, securing proprietary designs from competitors. the bit can only be erased in conjunction with the array during an erase cycle. electronic signature word an electronic signature word is provided in the palce16v8 device. it consists of 64 bits of programmable memory that can contain user-de?ned data. the signature data is always available to the user independent of the security bit. programming and erasing the palce16v8 can be programmed on standard logic programmers. it also may be erased to reset a previously con?gured device back to its unprogrammed state. erasure is automatically performed by the programming hardware. no special erase operation is required. quality and testability the palce16v8 offers a very high level of built-in quality. the erasability of the device provides a direct means of verifying performance of all ac and dc parameters. in addition, this veri?es complete programmability and functionality of the device to provide the highest programming yields and post-programming functional yields in the industry. technology the high-speed palce16v8 is fabricated with vantis advanced electrically-erasable (ee) cmos process. the array connections are formed with proven ee cells. inputs and outputs are designed to be compatible with ttl devices. this technology provides strong input clamp diodes, output slew-rate control, and a grounded substrate for clean switching. pci compliance palce16v8 devices in the -5/-7/-10 speed grades are fully compliant with the pci local bus speci?cation published by the pci special interest group. the palce16v8s predictable timing ensures compliance with the pci ac speci?cations independent of the design. zero-standby power mode the palce16v8z features a zero-standby power mode. when none of the inputs switch for an extended period (typically 50 ns), the palce16v8z will go into standby mode, shutting down
254 palce16v8 and palce16v8z families most of its internal circuitry. the current will go to almost zero (i cc < 15 a). the outputs will maintain the states held before the device went into the standby mode. there is no speed penalty associated with coming out of standby mode. when any input switches, the internal circuitry is fully enabled, and power consumption returns to normal. this feature results in considerable power savings for operation at low to medium frequencies. this saving is illustrated in the i cc vs. frequency graph. product-term disable on a programmed palce16v8z, any product terms that are not used are disabled. power is cut off from the product terms so that they do not draw current. as shown in the i cc vs. frequency graph, product-term disabling results in considerable power savings. this saving is greater at the higher frequencies. further hints on minimizing power consumption can be found in a separate document entitled, minimizing power consumption with zero-power plds .
palce16v8 and palce16v8z families 255 pal devices logic diagram 034781112151619202324272831 0 7 8 15 16 23 24 31 03478111215161920 24272831 23 i 2 i 1 clk/i 0 1 2 3 i 4 i 3 4 5 clk oe 1 1 0 x 1 0 sg1 sl0 7 1 1 0 x 1 0 sg1 sl0 5 1 1 0 x 1 0 sg1 sl0 4 sg1 1 1 0 x 1 0 dq q 1 0 1 1 1 1 1 0 0 0 0 1 v cc sl0 5 0 x sg1 1 1 0 x 1 0 dq q 1 0 1 1 1 1 1 0 0 0 0 1 v cc sl0 4 0 x 1 1 0 x 1 0 sg1 sl0 6 sg1 1 1 0 x 1 0 dq q 1 0 1 1 1 1 1 0 0 0 0 1 v cc sl0 6 0 x sg0 1 1 0 x 1 0 dq q 1 0 1 1 0 x 1 1 1 0 0 0 0 1 v cc 17 i/o 4 16 18 i/o 5 i/o 6 i/o 7 19 sl1 7 sl1 6 sl1 5 sl1 4 20 v cc sl0 7 16493e-2
256 palce16v8 and palce16v8z families logic diagram (continued) 034781112151619202324272831 32 39 40 47 48 55 0 3 4 7 8 1112 1516 1920 2324 2728 31 i 8 i 7 i 6 i 5 56 63 6 7 8 9 clk oe 1 1 0 x 1 0 sg1 sl0 3 1 1 0 x 1 0 sg1 sl0 1 1 1 0 x 1 0 sg1 sl0 0 1 1 0 x 1 0 sg1 sl0 2 oe/i 1 1 0 x 1 0 dq q 1 0 1 1 0 x 1 1 1 0 0 0 0 1 sg0 v cc sg1 1 1 0 x 1 0 dq q 1 0 1 1 1 1 1 0 0 0 0 1 v cc sl0 1 0 x 1 1 0 x 1 0 dq q 1 0 1 1 1 1 1 0 0 0 0 1 v cc 0 x sg1 1 1 0 x 1 0 dq q 1 0 1 1 1 1 1 0 0 0 0 1 v cc sl0 2 0 x sg1 sl0 3 i/o 3 15 i/o 2 14 i/o 1 13 i/o 0 12 11 sl1 3 sl1 2 sl1 1 sl1 0 9 sl0 0 gnd 10 16493e-6 (concluded)
palce16v8h-5/7 (coml) 257 pal devices absolute maximum ratings storage temperature . . . . . . . . . . . . . .-65 c to +150 c ambient temperature with power applied . . . . . . . . . . . . . .-55 c to +125 c supply voltage with respect to ground . . . . . . . . . . -0.5 v to +7.0 v dc input voltage . . . . . . . . . . . -0.5 v to v cc + 0.5 v dc output or i/o pin voltage . . . . . . . . . . . . . . . . . -0.5 v to v cc + 0.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2001 v latchup current (t a = 0 c to 75 c) . . . . . . . . . 100 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum rat- ings for extended periods may affect device reliability. pro- gramming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . . 0 c to +75 c supply voltage (v cc ) with respect to ground . . . . . . . . . +4.75 v to +5.25 v operating ranges de?ne those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges notes: 1. these are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. parameter symbol parameter description test description min max unit v oh output high voltage i oh = -3.2 ma, v in = v ih or v il , v cc = min 2.4 v v ol output low voltage i ol = 24 ma, v in = v ih or v il , v cc = min 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 1) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (note 1) 0.8 v i ih input high leakage current v in = 5.25 v, v cc = max (note 2) 10 a i il input low leakage current v in = 0 v, v cc = max (note 2) C100 a i ozh off-state output leakage current high v out = 5.25 v, v cc = max v in = v ih or v il (note 2) 10 a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 2) C100 a i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C150 ma i cc (static) supply current for -5 outputs open (i out = 0 ma), v in = 0 v v cc = max 125 ma i cc (dynamic) supply current for -7 outputs open (i out = 0 ma), v cc = max, f = 25 mhz 115 ma
258 palce16v8h-5/7 (coml) capacitance 1 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?ed whe re capacitance may be affected. switching characteristics over commercial operating ranges 1 notes: 1. see switching test circuit for test conditions. 2. output delay minimums for t pd , t co , t pzx , t pxz , t ea , and t er are de?ned under best case conditions. future process improvements may alter these values; therefore, minimum values are recommended for simulation purposes only. 3. skew testing takes into account pattern and switching direction differences between outputs that have equal loading. 4. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modi?ed wh ere frequency may be affected. 5. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) C t s . parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c, 5 pf c out output capacitance v out = 2.0 v f = 1 mhz 8 pf parameter symbol parameter description -5 -7 unit min 2 max min 2 max t pd input or feedback to combinatorial output 1 5 3 7.5 ns t s setup time from input or feedback to clock 3 5 ns t h hold time 0 0 ns t co clock to output 1415ns t skewr skew between registered outputs (note 3) 1 1 ns t wl clock width low 3 4 ns t wh high 3 4 ns f max maximum frequency (note 4) external feedback 1/(t s +t co ) 142.8 100 mhz internal feedback (f cnt ) 1/(t s +t cf ) (note 5) 166 125 mhz no feedback 1/(t wh +t wl ) 166 125 mhz t pzx oe to output enable 1616ns t pxz oe to output disable 1516ns t ea input to output enable using product term control 2639ns t er input to output disable using product term control 2539ns
palce16v8h-10 (coml, ind) 259 pal devices absolute maximum ratings storage temperature . . . . . . . . . . . . . .-65c to +150c ambient temperature with power applied . . . . . . . . . . . . . .-55c to +125c supply voltage with respect to ground . . . . . . . . . . -0.5 v to + 7.0 v dc input voltage . . . . . . . . . . . -0.5 v to v cc + 0.5 v dc output or i/o pin voltage . . . . . . . . . . . . . . . . . -0.5 v to v cc + 0.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2001 v latchup current (t a = -40c to +85c). . . . . . . 100 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum rat- ings for extended periods may affect device reliability. pro- gramming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . . 0c to +75c supply voltage (v cc ) with respect to ground . . . . . . . . . +4.75 v to +5.25 v industrial (i) devices temperature (t a ) operating in free air . . . . . . . . . . . . . . . . . . . . . . -40c to +85c supply voltage (v cc ) with respect to ground . . . . . . . . . . . +4.5 v to +5.5 v operating ranges de?ne those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial and industrial operating ranges notes: 1. these are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. parameter symbol parameter description test description min max unit v oh output high voltage i oh = C3.2 ma, v in = v ih or v il , v cc = min 2.4 v v ol output low voltage i ol = 24 ma, v in = v ih or v il , v cc = min 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 1) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (note 1) 0.8 v i ih input high leakage current v in = 5.25 v, v cc = max (note 2) 10 a i il input low leakage current v in = 0 v, v cc = max (note 2) C100 a i ozh off-state output leakage current high v out = 5.25 v, v cc = max v in = v ih or v il (note 2) 10 a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 2) C100 a i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C150 ma i cc (dynamic) commercial supply current outputs open (i out = 0 ma) v cc = max, f = 15 mhz 115 ma industrial supply current 130 ma
260 palce16v8h-10 (coml, ind) capacitance 1 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?ed whe re capacitance may be affected. switching characteristics over commercial and industrial operating ranges 1 notes: 1. see switching test circuit for test conditions. 2. output delay minimums for t pd , t co , t pzx , t pxz , t ea , and t er are de?ned under best case conditions. future process improvements may alter these values; therefore, minimum values are recommended for simulation purposes only. 3. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modi?ed wh ere frequency may be affected. 4. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) C t s . parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c, 5 pf c out output capacitance v out = 2.0 v f = 1 mhz 8 pf parameter symbol parameter description -10 unit min (note 2) max t pd input or feedback to combinatorial output 3 10 ns t s setup time from input or feedback to clock 7.5 ns t h hold time 0ns t co clock to output 3 7.5 ns t wl clock width low 6 ns t wh high 6 ns f max maximum frequency (note 3) external feedback 1/(t s +t co ) 66.7 mhz internal feedback (f cnt ) 1/(t s +t cf ) (note 4) 71.4 mhz no feedback 1/(t wh +t wl ) 83.3 mhz t pzx oe to output enable 210ns t pxz oe to output disable 210ns t ea input to output enable using product term control 3 10 ns t er input to output disable using product term control 3 10 ns
palce16v8q-10 (coml) 261 pal devices absolute maximum ratings storage temperature . . . . . . . . . . . . . .-65 c to +150 c ambient temperature with power applied . . . . . . . . . . . . . .-55 c to +125 c supply voltage with respect to ground . . . . . . . . . . -0.5 v to +7.0 v dc input voltage . . . . . . . . . . . -0.5 v to v cc + 0.5 v dc output or i/o pin voltage . . . . . . . . . . . . . . . . . -0.5 v to v cc + 0.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2001 v latchup current (t a = 0 c to 75 c) . . . . . . . . . 100 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum rat- ings for extended periods may affect device reliability. pro- gramming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . . 0 c to +75 c supply voltage (v cc ) with respect to ground . . . . . . . . . +4.75 v to +5.25 v operating ranges de?ne those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges notes: 1. these are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. parameter symbol parameter description test description min max unit v oh output high voltage i oh = -3.2 ma, v in = v ih or v il , v cc = min 2.4 v v ol output low voltage i ol = 24 ma, v in = v ih or v il , v cc = min 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 1) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (note 1) 0.8 v i ih input high leakage current v in = 5.25 v, v cc = max (note 2) 10 a i il input low leakage current v in = 0 v, v cc = max (note 2) C100 a i ozh off-state output leakage current high v out = 5.25 v, v cc = max v in = v ih or v il (note 2) 10 a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 2) C100 a i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C150 ma i cc supply current (dynamic) outputs open (i out = 0 ma), v cc = max, f = 15 mhz 55 ma
262 palce16v8q-10 (coml) capacitance 1 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?ed whe re capacitance may be affected. switching characteristics over commercial operating ranges 1 notes: 1. see switching test circuit for test conditions. 2. output delay minimums for t pd , t co , t pzx , t pxz , t ea , and t er are de?ned under best case conditions. future process improvements may alter these values; therefore, minimum values are recommended for simulation purposes only. 3. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modi?ed wh ere frequency may be affected. 4. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) C t s . parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c, 5 pf c out output capacitance v out = 2.0 v f = 1 mhz 8 pf parameter symbol parameter description -10 unit min 2 max t pd input or feedback to combinatorial output 3 10 ns t s setup time from input or feedback to clock 7.5 ns t h hold time 0ns t co clock to output 3 7.5 ns t wl clock width low 6 ns t wh high 6 ns f max maximum frequency (note 3) external feedback 1/(t s +t co ) 66.7 mhz internal feedback (f cnt ) 1/(t s +t cf ) (note 4) 71.4 mhz no feedback 1/(t wh +t wl ) 83.3 mhz t pzx oe to output enable 210ns t pxz oe to output disable 210ns t ea input to output enable using product term control 3 10 ns t er input to output disable using product term control 3 10 ns
palce16v8h-15/25, q-15/25 (coml, ind), q-20 (ind) 263 pal devices absolute maximum ratings storage temperature . . . . . . . . . . . . . .-65c to +150c ambient temperature with power applied . . . . . . . . . . . . . .-55c to +125c supply voltage with respect to ground . . . . . . . . . . -0.5 v to + 7.0 v dc input voltage . . . . . . . . . . . -0.5 v to v cc + 0.5 v dc output or i/o pin voltage . . . . . . . . . . . . . . . . . -0.5 v to v cc + 0.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2001 v latchup current (t a = -40c to +85c). . . . . . . 100 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum rat- ings for extended periods may affect device reliability. pro- gramming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . . 0c to +75c supply voltage (v cc ) with respect to ground . . . . . . . . . +4.75 v to +5.25 v industrial (i) devices temperature (t a ) operating in free air . . . . . . . . . . . . . . . . . . . . . . -40c to +85c supply voltage (v cc ) with respect to ground . . . . . . . . . . . +4.5 v to +5.5 v operating ranges de?ne those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial and industrial operating ranges notes: 1. these are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. parameter symbol parameter description test description min max unit v oh output high voltage i oh = C3.2 ma, v in = v ih or v il , v cc = min 2.4 v v ol output low voltage i ol = 24 ma, v in = v ih or v il , v cc = min 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 1) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (note 1) 0.8 v i ih input high leakage current v in = 5.25 v, v cc = max (note 2) 10 a i il input low leakage current v in = 0 v, v cc = max (note 2) C100 a i ozh off-state output leakage current high v out = 5.25 v, v cc = max v in = v ih or v il (note 2) 10 a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 2) C100 a i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C150 ma i cc (dynamic) commercial supply current outputs open (i out = 0 ma) v cc = max, f = 15 mhz h90 ma q55 industrial supply current h 130 ma q65
264 palce16v8h-15/25, q-15/25 (coml, ind), q-20 (ind) capacitance 1 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?ed whe re capacitance may be affected. switching characteristics over commercial and industrial operating ranges 1 notes: 1. see switching test circuit for test conditions. 2. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modi?ed wh ere frequency may be affected. 3. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) C t s . parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c, 5 pf c out output capacitance v out = 2.0 v f = 1 mhz 8 pf parameter symbol parameter description -15 -20 -25 unit min max min max min max t pd input or feedback to combinatorial output 15 20 25 ns t s setup time from input or feedback to clock 12 13 15 ns t h hold time 0 0 0 ns t co clock to output 10 11 12 ns t wl clock width low 8 10 12 ns t wh high 8 10 12 ns f max maximum frequency (note 2) external feedback 1/(t s +t co ) 45.5 41.6 37 mhz internal feedback (f cnt ) 1/(t s +t cf ) (note 3) 50 45.4 40 mhz no feedback 1/(t wh +t wl ) 62.5 50.0 41.6 mhz t pzx oe to output enable 15 18 20 ns t pxz oe to output disable 15 18 20 ns t ea input to output enable using product term control 15 18 20 ns t er input to output disable using product term control 15 18 20 ns
palce16v8z-12 (ind) 265 pal devices absolute maximum ratings storage temperature . . . . . . . . . . . . . .-65c to +150c ambient temperature with power applied . . . . . . . . . . . . . .-55c to +125c supply voltage with respect to ground . . . . . . . . . . -0.5 v to + 7.0 v dc input voltage . . . . . . . . . . . -0.5 v to v cc + 0.5 v dc output or i/o pin voltage . . . -0.5 v to v cc + 0.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2001 v latchup current (t a = -40c to +85c). . . . . . . 100 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum rat- ings for extended periods may affect device reliability. pro- gramming conditions may differ. operating ranges industrial (i) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . -40c to +85c supply voltage (v cc ) with respect to ground . . . . . . . . . . . +4.5 v to +5.5 v operating ranges de?ne those limits between which the func- tionality of the device is guaranteed. dc characteristics over industrial operating ranges notes: 1. these are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. represents the worst case of hc and hct standards, allowing compatibility with either. 3. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 4. not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. parameter symbol parameter description test description min max unit v oh output high voltage v in = v ih or v il , v cc = min i oh = 6 ma 3.84 v i oh = 20 a v cc C 0.1 v v v ol output low voltage v in = v ih or v il , v cc = min i ol = 24 ma 0.5 v i ol = 6 ma 0.33 v i ol = 20 a 0.1 v v ih input high voltage guaranteed input logical high voltage for all inputs (notes 1 and 2) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (notes 1 and 2) 0.9 v i ih input high leakage current v in = 5.25 v, v cc = max (note 3) 10 a i il input low leakage current v in = 0 v, v cc = max (note 3) C10 a i ozh off-state output leakage current high v out = 5.25 v, v cc = max v in = v ih or v il (note 3) 10 a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 3) C10 a i sc output short-circuit current v out = 0.5 v, v cc = max (note 4) C30 C150 ma i cc supply current (static) outputs open (i out = 0 ma) v cc = max f = 0 mhz 30 a supply current (dynamic) f = 15 mhz 75 ma
266 palce16v8z-12 (ind) capacitance 1 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?ed whe re capacitance may be affected. switching characteristics over industrial operating ranges 1 notes: 1. see switching test circuit for test conditions. 2. this parameter is tested in standby mode. 3. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modi?ed wh ere frequency may be affected. 4. output delay minimums for t pd , t co , t pzx , t pxz , t ea , and t er are de?ned under best case conditions. future process improvements may alter these values therefore, minimum values are recommended for simulation purposes only. 5. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) C t s . parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c, 5 pf c out output capacitance v out = 2.0 v f = 1 mhz 8 pf parameter symbol parameter description -12 unit min max t pd input or feedback to combinatorial output (note 2) 12 ns t s setup time from input or feedback to clock 8ns t h hold time 0ns t co clock to output 8ns t wl clock width low 5ns t wh high 5ns f max maximum frequency (notes 3 and 4) external feedback 1/(t s +t co ) 62.5 mhz internal feedback (f cnt ) 1/(t s +t cf ) 77 mhz no feedback 1/(t wh +t wl ) 100 mhz t pzx oe to output enable 8ns t pxz oe to output disable 8ns t ea input to output enable using product term control 13 ns t er input to output disable using product term control 13 ns
palce16v8z-15 (ind) 267 pal devices absolute maximum ratings storage temperature . . . . . . . . . . . . . .-65c to +150c ambient temperature with power applied . . . . . . . . . . . . . .-55c to +125c supply voltage with respect to ground . . . . . . . . . . -0.5 v to + 7.0 v dc input voltage . . . . . . . . . . . -0.5 v to v cc + 0.5 v dc output or i/o pin voltage . . . -0.5 v to v cc + 0.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2001 v latchup current (t a = -40c to +85c). . . . . . . 100 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum rat- ings for extended periods may affect device reliability. pro- gramming conditions may differ. operating ranges industrial (i) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . -40c to +85c supply voltage (v cc ) with respect to ground . . . . . . . . . . . +4.5 v to +5.5 v operating ranges de?ne those limits between which the func- tionality of the device is guaranteed. dc characteristics over industrial operating ranges notes: 1. these are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. represents the worst case of hc and hct standards, allowing compatibility with either. 3. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 4. not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. parameter symbol parameter description test description min max unit v oh output high voltage v in = v ih or v il , v cc = min i oh = 6 ma 3.84 v i oh = 20 a v cc C 0.1 v v v ol output low voltage v in = v ih or v il , v cc = min i ol = 24 ma 0.5 v i ol = 6 ma 0.33 v i ol = 20 a 0.1 v v ih input high voltage guaranteed input logical high voltage for all inputs (notes 1 and 2) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (notes 1 and 2) 0.9 v i ih input high leakage current v in = 5.25 v, v cc = max (note 3) 10 a i il input low leakage current v in = 0 v, v cc = max (note 3) C10 a i ozh off-state output leakage current high v out = 5.25 v, v cc = max v in = v ih or v il (note 3) 10 a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 3) C10 a i sc output short-circuit current v out = 0.5 v, v cc = max (note 4) C30 C150 ma i cc supply current (static) outputs open (i out = 0 ma) v cc = max f = 0 mhz 15 a supply current (dynamic) f = 25 mhz 75 ma
268 palce16v8z-15 (ind) capacitance 1 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?ed whe re capacitance may be affected. switching characteristics over industrial operating ranges 1 notes: 1. see switching test circuit for test conditions. 2. this parameter is tested in standby mode. 3. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modi?ed wh ere frequency may be affected. 4. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) C t s . parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c, 5 pf c out output capacitance v out = 2.0 v f = 1 mhz 8 pf parameter symbol parameter description -15 unit min 2 max t pd input or feedback to combinatorial output 15 ns t s setup time from input or feedback to clock 10 ns t h hold time 0ns t co clock to output 10 ns t wl clock width low 8 ns t wh high 8 ns f max maximum frequency (notes 3 and 4) external feedback 1/(t s +t co ) 50 mhz internal feedback (f cnt ) 1/(t s +t cf ) 58.8 mhz no feedback 1/(t wh +t wl ) 62.5 mhz t pzx oe to output enable 15 ns t pxz oe to output disable 15 ns t ea input to output enable using product term control 15 ns t er input to output disable using product term control 15 ns
palce16v8z-25 (coml, ind) 269 pal devices absolute maximum ratings storage temperature . . . . . . . . . . . . . .-65c to +150c ambient temperature with power applied . . . . . . . . . . . . . .-55c to +125c supply voltage with respect to ground . . . . . . . . . . -0.5 v to + 7.0 v dc input voltage . . . . . . . . . . . -0.5 v to v cc + 0.5 v dc output or i/o pin voltage . . . -0.5 v to v cc + 0.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2001 v latchup current (t a = -40c to +85c). . . . . . . 100 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum rat- ings for extended periods may affect device reliability. pro- gramming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . . 0c to +75c supply voltage (v cc ) with respect to ground . . . . . . . . . +4.75 v to +5.25 v industrial (i) devices temperature (t a ) operating in free air . . . . . . . . . . . . . . . . . . . . . . -40c to +85c supply voltage (v cc ) with respect to ground . . . . . . . . . . . +4.5 v to +5.5 v operating ranges de?ne those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial and industrial operating ranges notes: 1. these are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. represents the worst case of hc and hct standards, allowing compatibility with either. 3. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 4. not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. parameter symbol parameter description test description min max unit v oh output high voltage v in = v ih or v il , v cc = min i oh = 6 ma 3.84 v i oh = 20 a v cc C 0.1 v v v ol output low voltage v in = v ih or v il , v cc = min i ol = 24 ma 0.5 v i ol = 6 ma 0.33 v i ol = 20 a 0.1 v v ih input high voltage guaranteed input logical high voltage for all inputs (notes 1 and 2) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (notes 1 and 2) 0.9 v i ih input high leakage current v in = 5.25 v, v cc = max (note 3) 10 a i il input low leakage current v in = 0 v, v cc = max (note 3) C10 a i ozh off-state output leakage current high v out = 5.25 v, v cc = max v in = v ih or v il (note 3) 10 a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 3) C10 a i sc output short-circuit current v out = 0.5 v, v cc = max (note 4) C30 C150 ma i cc supply current (static) outputs open (i out = 0 ma) v cc = max f = 0 mhz 15 a supply current (dynamic) f = 25 mhz 90 ma
270 palce16v8z-25 (coml, ind) capacitance 1 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?ed whe re capacitance may be affected. switching characteristics over commercial and industrial operating ranges 1 notes: 1. see switching test circuit for test conditions. 2. this parameter is tested in standby mode. 3. this parameter is tested in standby mode. when the device is not in standby mode, the t pd will typically be 2 ns faster. 4. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modi?ed wh ere frequency may be affected. 5. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) C t s . parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c, 5 pf c out output capacitance v out = 2.0 v f = 1 mhz 8 pf parameter symbol parameter description -25 unit min 2 max t pd input or feedback to combinatorial output (note 3) 25 ns t s setup time from input or feedback to clock 20 ns t h hold time 0ns t co clock to output 10 ns t wl clock width low 8ns t wh high 8ns f max maximum frequency (notes 4 and 5) external feedback 1/(t s +t co ) 33.3 mhz internal feedback (f cnt ) 1/(t s +t cf ) 50 mhz no feedback 1/(t wh +t wl ) 50 mhz t pzx oe to output enable 25 ns t pxz oe to output disable 25 ns t ea input to output enable using product term control 25 ns t er input to output disable using product term control 25 ns
palce16v8 and palce16v8z families 271 pal devices switching waveforms notes: 1. v t = 1.5 v 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 ns to 5 ns typical. t pd input or feedback combinatorial output v t v t a. combinatorial output 16493e-3 t wh clock c. clock width v t t wl 16493e-4 v t input or feedback registered output b. registered output t s t co v t t h v t clock 16493e-5 v t v t input output d. input to output disable/enable t er t ea v oh C 0.5v v ol + 0.5v 16493e-6 16493e-7 v t v t oe output e. oe to output disable/enable t pzx t pxz v oh C 0.5v v ol + 0.5v
272 palce16v8 and palce16v8z families key to switching waveforms switching test circuit must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs ks000010-pal speci?cation s 1 c l commercial measured output value r 1 r 2 t pd , t co closed 50 pf 200 w 390 w 1.5 v t ea z ? h: open 1.5 v z ? l: closed t er h ? z: open 5 pf h-5: 200 w h ? z: v oh C 0.5 v l ? z: closed l ? z: v ol + 0.5 v c l output r 1 r 2 s 1 test point 5 v 16493e-8
palce16v8 and palce16v8z families 273 pal devices typical i cc characteristics v cc = 5 v, t a = 25c i cc vs. frequency the selected typical pattern utilized 50% of the device resources. half of the macrocells were programmed as registered, and the other half were programmed as combinatorial. half of the available product terms were used for each macrocell. on any vector, h alf of the outputs were switching. by utilizing 50% of the device, a midpoint is de?ned for i cc . from this midpoint, a designer may scale the i cc graphs up or down to estimate the i cc requirements for a particular design. 150 125 100 75 50 25 0 01020304050 frequency (mhz) i cc (ma) 16v8h-5 16v8h-7 16v8h-10 16v8h-15/25 16v8q-10/15/25 16493e-9 16v8z-12/15 16v8z-25
274 palce16v8 and palce16v8z families endurance characteristics the palce16v8 is manufactured using vantis advanced electrically-erasable (ee) cmos process. this technology uses an ee cell to replace the fuse link used in bipolar parts. as a result, the device can be erased and reprogrammeda feature which allows 100% testing at the factory. robustness features palce16v8x-x/5 devices have some unique features that make them extremely robust, especially when operating in high-speed design environments. pull-up resistors on inputs and i/o pins cause unconnected pins to default to a known state. input clamping circuitry limits negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing. a special noise ?lter makes the programming circuitry completely insensitive to any positive overshoot that has a pulse width of less than about 100 ns for the /5 versions. selected /4 devices are also being retro?tted with these robustness features. input/output equivalent schematics for palce16v8 symbol parameter test conditions value unit t dr min pattern data retention time max storage temperature 10 years max operating temperature 20 years n min reprogramming cycles normal programming conditions 100 cycles 16493e-10 typical input typical output preload circuitry esd protection and clamping feedback input v cc v cc > 50 k w v c c programming voltage detection positive overshoot filter programming circuitry provides esd protection and clamping programming pins only > 50 k w v cc
palce16v8 and palce16v8z families 275 pal devices input/output equivalent schematics for palce16v8z power-up reset the palce16v8 has been designed with the capability to reset during system power-up. following power-up, all ?ip-?ops will be reset to low. the output state will be high independent of the logic polarity. this feature provides extra ?exibility to the designer and is especially valuable in simplifying state machine initialization. a timing diagram and parameter table are shown below. due to the synchronous operation of the power-up reset and the wide range of ways v cc can rise to its steady state, two conditions are required to ensure a valid power-up reset. these conditions are: u the v cc rise must be monotonic. u following reset, the clock input must not be driven from low to high until all applicable input and feedback setup times are met. parameter symbol parameter descriptions min max unit t pr power-up reset time 1000 ns t s input or feedback setup time see switching characteristics t wl clock width low 16493e-11 typical input typical output feedback input esd protection and clamping input transition detection v cc v cc programming voltage detection positive overshoot filter programming circuitry provides esd protection and clamping programming pins only input transition detection preload circuitry
276 palce16v8 and palce16v8z families typical thermal characteristics measured at 25 c ambient. these parameters are not tested. plastic q jc considerations the data listed for plastic q jc are for reference only and are not recommended for use in calculating junction temperatures. the heat-?ow paths in plastic-encapsulated devices are complex, making the q jc measurement relative to a speci?c location on the pack- age surface. tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. furthermore, q jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant tem- perature. therefore, the measurements can only be used in a similar environment. parameter symbol parameter description typ unit pdid plcc q jc thermal impedance, junction to case 25 22 c/w q ja thermal impedance, junction to ambient 71 64 c/w q jma thermal impedance, junction to ambient with air ?ow 200 lfpm air 61 55 c/w 400 lfpm air 55 51 c/w 600 lfpm air 51 47 c/w 800 lfpm air 47 45 c/w figure 3. power-up reset waveform t pr t wl t s 4 v v cc power registered output clock 16493e-12
palce16v8 and palce16v8z families 277 pal devices connection diagrams top view pin designations clk = clock gnd = ground i = input i/o = input/output oe = output enable v cc = supply voltage dip/soic note: pin 1 is marked for orientation. plcc 1 2 3 4 5 6 7 8 9 10 clk/i 0 i 1 i 2 i 3 i 4 i 5 i 6 i 7 i 8 gnd v cc i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 oe /i 9 20 19 18 17 16 15 14 13 12 11 16493e-9 1 20 19 18 17 16 15 14 2 3 4 5 6 7 8 9 10 11 12 13 i 3 i 4 i 5 i 6 i 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 oe/i 9 i/o 0 i/o 1 gnd i 8 clk/i 0 v cc i/o 7 i 1 i 2 16493e-10
278 palce16v8 and palce16v8z families ordering information commercial and industrial products vantis programmable logic products for commercial and industrial applications are available with several ordering options. the order number (valid combination) is formed by a combination of: valid combinations valid combinations lists con?gurations planned to be supported in volume for this device. consult the local vantis sales of?ce to con?rm availability of speci?c valid combinations and to check on newly released combinations. package type p = 20-pin plastic dip (pd 020) j = 20-pin plastic leaded chip carrier (pl 020) s = 20-pin plastic gull-wing small outline package (so 020) operating conditions c = commercial (0 c to +75 c) i = industrial (-40 c to +85 c) pa l c e 1 6 v 8 h - 5 j c speed -5 = 5 ns t pd -7 = 7.5 ns t pd -10 = 10 ns t pd -12 = 12 ns t pd -15 = 15 ns t pd -20 = 20 ns t pd -25 = 25 ns t pd family type pal = programmable array logic power h = half power (90C125 ma i cc ) q = quarter power (55 ma i cc ) z = zero power (15 a i cc standby) technology ce = cmos electrically erasable number of array inputs output type v = versatile number of outputs /5 programming designator blank = initial algorithm /4 = first revision /5 = second revision (same algorithm as /4) valid combinations palce16v8h-5 jc /5 palce16v8h-7 pc, jc, sc palce16v8h-10 pc, jc, sc, pi, ji /4 palce16v8q-10 jc /5 palce16v8h-15 pc, jc, sc /4 palce16v8q-15 pc, jc palce16v8q-20 pi, ji palce16v8h-25 pc, jc, sc, pi, ji palce16v8q-25 pc, jc, pi, ji palce16v8z-12 pi, ji palce16v8z-15 palce16v8z-25 pc, jc, sc, pi, ji, si

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